| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3212
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-283 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 |
| filingDate |
2014-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bffd1edcf314eab2d0adf27fd600dc66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc59c2b7300140f04f2b2bdffa8643a0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_858b89c57c0d4bac68cc3bfbec553e8f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6ba5813d192c81e50756d438b82a3449 |
| publicationDate |
2016-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016181392-A1 |
| titleOfInvention |
Partial spacer for increasing self aligned contact process margins |
| abstract |
A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9799741-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11004795-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10090249-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10643947-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017179245-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017178975-A1 |
| priorityDate |
2014-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |