http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016172236-A1
Outgoing Links
Predicate | Object |
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assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bf83328d853bc7476ca10212837b3a01 |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76229 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
filingDate | 2014-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_56ba4efdf08d8dcae8af1cc8f2a0cee0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_894acc379f687dc0f7855c108a0b0c71 |
publicationDate | 2016-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | US-2016172236-A1 |
titleOfInvention | Device substrates, integrated circuits and methods for fabricating device substrates and integrated circuits |
abstract | Integrated circuits and methods for fabricating device substrates and integrated circuits are provided. Integrated circuits in accordance with those described herein include a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region. The integrated circuits also have semiconductor devices thereon with isolation trenches in between them. The corners of the trenches in MV and HV regions of the integrated circuit are more rounded than the corners of the trenches in the LV region so that interference by trench corners in the MV and HV regions with the operation and performance of adjacent MV or HV device is minimized. Methods for fabricating such integrated circuits, as well as device substrates from which such integrated circuits may be fabricated, involve providing a semiconductor substrate and overlaying various oxide layers thereon, along with performing nitride pullback techniques, and forming isolation trenches by shallow trench isolation techniques to form trench corners in MV and HV regions that are more rounded than trench corners in the LV region. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11367721-B2 |
priorityDate | 2014-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Predicate | Subject |
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isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6518146-B1 |
isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419579069 |
Total number of triples: 21.