| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f47985b7c371b565f319708450999686 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45182
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45036
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2200-303
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45676
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45702
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45188
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45674
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45184
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2200-75
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45722
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45202 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F3-45385
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-6871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F3-45188
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-687 |
| filingDate |
2015-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_084cc4430927d5dbfe7f3e803f7250e7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_721bdcfbde595c381a6c197eaed0b78e |
| publicationDate |
2016-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016164517-A1 |
| titleOfInvention |
High Gain Load Circuit for a Differential Pair Using Depletion Mode Transistors |
| abstract |
A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10911045-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102019120354-B3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102019120355-B3 |
| priorityDate |
2014-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |