| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28291
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28158
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-516
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2016-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3ef6fc49830ca080195e9d1f84b101c2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c84f08f39d435e569b024a1c6c235b35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_37ca468a90e8068b98bae2790c0f898f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a743b81786753d39675075cb1d921aa |
| publicationDate |
2016-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016163821-A1 |
| titleOfInvention |
Semiconductor structure including a ferroelectric transistor and method for the formation thereof |
| abstract |
A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11004868-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2018174865-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9793397-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10672881-B2 |
| priorityDate |
2014-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |