http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016124810-A1

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publicationDate 2016-05-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2016124810-A1
titleOfInvention 3d memory with error checking and correction function
abstract An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9570200-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019139968-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11315657-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016042811-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10740177-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10628324-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11321166-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11532634-B2
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