| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c1e3d8364bf64e4ac6e1a9cd5df2bd54 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76864
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48 |
| filingDate |
2015-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20425f5172b7218d766f7bd8f8e17f30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da076b2197187ec4dab0b3922950731a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4f0f09c0087957669b0b15d0deb82ec3 |
| publicationDate |
2016-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016111351-A1 |
| titleOfInvention |
Solution for tsv substrate leakage |
| abstract |
A semiconductor device manufacturing method includes providing a wafer, which includes a semiconductor substrate, a semiconductor device located on the semiconductor substrate, an interlayer dielectric layer covering the semiconductor device, and a through hole penetrating through the interlayer dielectric layer and a portion of the semiconductor substrate. A metal layer is formed inside the through hole and on a surface of the interlayer dielectric layer. A first planarization process is conducted to remove a portion of the metal layer on the surface of the interlayer dielectric layer. The method also includes conducting an annealing alloy treatment and conducting a second planarization process to completely remove the metal layer on the surface of the interlayer dielectric layer. The manufacturing methods can slowly release stress of the wafer and effectively prevent cracks in silicon vias, thereby reducing TSV leakage problems, thus improving the reliability and yield of the devices. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022020675-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10643926-B2 |
| priorityDate |
2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |