http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016110126-A1

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publicationDate 2016-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2016110126-A1
titleOfInvention All-flash-array primary storage and caching appliances implementing triple-level cell (tlc)-nand semiconductor microchps
abstract A computer-implemented method for storing and caching data in an all-flash-array includes erasing a TLC-NAND flash cell and programming the cell with a binary value multiple times in sequence corresponding to multiple sequential stages between erasures. The method also includes processing the binary value in relation to a respective threshold voltage at each of the multiple sequential stages. The method further includes storing metadata corresponding to a current stage associated with the number of times the TLC-NAND flash cell has been programmed since being erased.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019006012-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020150873-A1
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