| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76855 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02057
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78651
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41766
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2015-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a47c1900ea21f1b781c081cd471e64d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_efa68f948065e3b948adab4c5819b4b4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ebb7819b8134921d689ba354000566eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_db0c359b5b5d34ff47570bee990a3d2e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c618b1e7d61abaf87b034cfbd217e060 |
| publicationDate |
2016-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016087078-A1 |
| titleOfInvention |
MOS Devices Having Epitaxy Regions with Reduced Facets |
| abstract |
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021233771-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015076621-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9502404-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11004976-B2 |
| priorityDate |
2013-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |