| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c1e3d8364bf64e4ac6e1a9cd5df2bd54 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28035
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2015-07-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2dfc864c7bd6eece82b67661d17ed872
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_84988d310a00b80ffdda8fe5c70649da |
| publicationDate |
2016-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016056082-A1 |
| titleOfInvention |
Chemical mechanical polishing method for first interlayer dielectric layer |
| abstract |
A method for manufacturing a semiconductor device includes providing a semiconductor substrate comprising a low-density region and a high-density region, forming a first gate structure in the low-density region and a second gate structure in the high-density region, form an etch stop layer on the first and second gate structures, and forming an interlayer dielectric layer on the etch stop layer and on the semiconductor substrate. The method further includes performing a first chemical mechanical polishing (CMP) process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the first gate structure, performing a second CMP process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the second gate structure, and performing a third CMP process to completely remove the etch stop layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017040436-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10056466-B2 |
| priorityDate |
2014-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |