| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 |
| filingDate |
2015-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c539cdc4e52be2e966028227aeed4a42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52c780cbb55ff4c25fb13cb6b596129f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93827ef0ecf43c79033a9c634bf37b8c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_858b89c57c0d4bac68cc3bfbec553e8f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_067f8d20a971eab0829de790db404977
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e24ee7aa6294abecea582441d1f118de |
| publicationDate |
2016-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016027893-A1 |
| titleOfInvention |
Multiple thickness gate dielectrics for replacement gate field effect transistors |
| abstract |
After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I795378-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10050033-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I756283-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10790279-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11715639-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10510750-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11302691-B2 |
| priorityDate |
2014-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |