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filingDate 2015-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2016-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2016004639-A1
titleOfInvention System and method for a cache in a multi-core processor
abstract The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2017171974-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10185619-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2018112340-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11681567-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023090429-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11321146-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018173625-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11157407-B2
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