| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2201-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7782
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0619
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0683
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1458 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 |
| filingDate |
2015-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3658d963980ac56df4d6be5a7643d15d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f44ea9ad1f35d46fdc58c55596dd477b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_623ccd5fa71068a772b5356d0b0eaade
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a2fd1bfdbdbb0db4833ee30c2e4fbdec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_718235ae4820b0c972cebc03af3e925f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_71aa3b9d616efa9d4f3d1ae5d1e97710 |
| publicationDate |
2015-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015363136-A1 |
| titleOfInvention |
Semiconductor device and electronic device |
| abstract |
A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021343936-A1 |
| priorityDate |
2014-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |