http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015294993-A1

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filingDate 2014-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be1fd3bd1bc4dcdd6b28849f5a95cecd
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publicationDate 2015-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2015294993-A1
titleOfInvention Array substrate and manufacturing method thereof, display device
abstract An array substrate and a manufacturing method thereof as well as a display device are disclosed. The array substrate includes a gate ( 21 ) and a gate insulating layers ( 22 ) of TFT formed in this order on a surface of a base substrate ( 20 ); a semiconductor active layer ( 23 ), an etching stop layer ( 24 ), and a source ( 251 )/drain ( 252 ) of the TFT formed in this order on a surface of the gate insulating layer ( 22 ) corresponding to the gate ( 21 ) of the TFT. The source ( 251 ) and drain ( 252 ) of the TFT contact the semiconductor active layer ( 23 ) through respective vias. The array substrate further includes: a shielding electrode ( 26 ) formed between the gate ( 21 ) of the TFT and the base substrate ( 20 ); and an insulating layer ( 27 ) formed between the gate ( 21 ) of the TFT and the shielding electrode ( 26 ). In a region where the gate ( 21 ) faces the source ( 251 ), the area of the gate ( 210 ) is smaller than that of the source ( 251 ); and/or in a region where the gate ( 21 ) faces the drain ( 252 ), the area of the gate ( 210 ) is smaller than that of the drain ( 252 ). The array substrate according to embodiments of the present invention reduces the parasitic capacitance between the source/drain and the gate of the TFT and improves the quality of a display device.
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priorityDate 2013-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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