| abstract |
A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar. |