| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5384
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76811
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-027 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
2015-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fdb1a5c527acc2f0ad7ad29ddd69893
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c026e017be4ff5fd27037cc25a9ea590 |
| publicationDate |
2015-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015262934-A1 |
| titleOfInvention |
Patterning Approach to Reduce Via to Via Minimum Spacing |
| abstract |
A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches. |
| priorityDate |
2013-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |