| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7a4ba732e996ccb96709867320c92feb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L2207-50 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0994
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0818
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2014-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3dd44a167f74b4a0fd2edcf4bfc8467b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4432d25dd1903dac89bdd275274479d1 |
| publicationDate |
2015-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015255129-A1 |
| titleOfInvention |
Method for performing memory interface control of an electronic device, and associated apparatus |
| abstract |
A method for performing memory interface control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of a memory interface circuit of the electronic device, and the memory interface circuit is arranged for controlling a random access memory (RAM) of the electronic device; applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the memory interface circuit is calibrated with aid of the at least one phase shift. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11169191-B2 |
| priorityDate |
2014-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |