| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06K19-073
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06K19-0723
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-073
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-07 |
| filingDate |
2014-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5a337bc848e9ad335a629201ceecead6 |
| publicationDate |
2015-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015053775-A1 |
| titleOfInvention |
Integrated circuit and manufacturing method thereof |
| abstract |
An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016163359-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9990962-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10446560-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10410722-B2 |
| priorityDate |
2006-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |