| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e2c321c5b9b5774498f194d959bdf9df |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-562
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02241
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-564
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3192 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate |
2013-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7715c0b00b6f1cbfc65da3193109eed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e77d52f67f6cd92a2236bbf87d30729b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_79991ea56b7f4f98c64f9d48e47b2139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d8a32283055d1b2677c44575a17661c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b2f0ef24aa201ed069d60926185262d |
| publicationDate |
2015-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015048484-A1 |
| titleOfInvention |
Passivation for Group III-V Semiconductor Devices Having a Plated Metal Layer over an Interlayer Dielectric Layer |
| abstract |
A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9881847-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021328103-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018067633-A |
| priorityDate |
2013-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |