| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c943ee5f76f0b8cdffeb12667b59f37e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05647
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-16195
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1461
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-05042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-16235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01029
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01082
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01013
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05624 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3192
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-498
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-498 |
| filingDate |
2014-07-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_60bce7e3ecb2f61b072ca98ccddf8c0d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_286d9f41ed30a8b5066d2f541d095d26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c862be450aebc93f20d8d9a38d115c1 |
| publicationDate |
2014-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2014332985-A1 |
| titleOfInvention |
Chip package and manufacturing method thereof |
| abstract |
A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer. |
| priorityDate |
2009-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |