| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca748d5cbfb6d9d2f2c6013230fccd73 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0466
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3427
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-34 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34 |
| filingDate |
2014-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_574bb03576b40f36c5a618582e16f3ac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0613dd921c9d58a27a1a19801a5d2144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_726608d1a2b6985ac5c0084b091acf4d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_153a3c281fc17f5f93f1559f73f06b13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac776c3c974d903aac5dafc86943adf3 |
| publicationDate |
2014-10-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2014301139-A1 |
| titleOfInvention |
Method to Reduce Program Disturbs in Non-Volatile Memory Cells |
| abstract |
A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V NEG ) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10269396-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10026460-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2017171979-A1 |
| priorityDate |
2013-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |