| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1469
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14634 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146 |
| filingDate |
2013-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_577f426b7cb6d9064020b02bfdaf844e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_120eb47d21b34ef9e8b55fad42db900c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c9cbe3f7248e6950215bc2f6497a3eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3150d2f7928f92d42d77358e68c1d518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3046aa8af7c6ee20d82a52946651158f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99c1055990e4242b1aeefa2ad4a6bf7e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ce939a207af950aac141a2a5bfac747 |
| publicationDate |
2014-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2014264682-A1 |
| titleOfInvention |
Interconnect Sructure for Stacked Device and Method |
| abstract |
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9865645-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9842855-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9461114-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10535706-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9449950-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11018179-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10861899-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10433435-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10157959-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017309636-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11552116-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015294956-A1 |
| priorityDate |
2013-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |