Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66825 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7881 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
filingDate |
2013-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1c18b5dfd279df7e49e65a4779912c98 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d55c8ad4ce713ad1a6a8d7439164c6c2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8cf2958c91ef6540badbceb602ff0d9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_095be0b32557a0f21c5666e030733b0d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_10ca4123ee48b0f034d149e527a3f3e6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef77cf20605abb62ff40ae1781b7aaed http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b772c040139703630da0a69f4f25e510 |
publicationDate |
2014-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2014239368-A1 |
titleOfInvention |
Semiconductor storage device and method of manufacturing the same |
abstract |
A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film. The second isolation region includes a second trench and a second element isolation insulating film filled in the second trench. The first and the second element isolation insulating films have different properties. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9293360-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016351435-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102373816-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9779983-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014295641-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20170018165-A |
priorityDate |
2013-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |