| abstract |
A testable integrated circuit chip ( 80, 100 ) includes a functional circuit ( 80 ) having modules (IP.i), a storage circuit ( 110 ) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller ( 140, 150 ) coupled with said storage circuit ( 110 ) and with said functional circuit modules (IP.i), said test controller ( 140, 150 ) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed. |