| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F5-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3887
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3004 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F5-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
| filingDate |
2012-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b886f8e0ff0a97fc58ca8a5858b29db
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b565499ad9299e9b5f4c99359f2af88
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf9a252c2944536e501a83ea7152f745
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d58f6a87e050b393786b92fa327ed078 |
| publicationDate |
2014-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2014149657-A1 |
| titleOfInvention |
Intelligent parametric scratchap memory architecture |
| abstract |
An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11132296-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022081784-A1 |
| priorityDate |
2012-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |