http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014110716-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a62555ff12316a9a118542896b4c0af7 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4908 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate | 2013-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09b95defab9bbf3bb95ff3d976d67b93 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7d09ec0cb1d163e7129b2f01fd6d5de9 |
| publicationDate | 2014-04-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2014110716-A1 |
| titleOfInvention | Thin Film Transistor and Manufacturing Method Thereof, an Array Substrate and a Display Device |
| abstract | Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the electrical performance of the thin film transistor and improve the picture quality of images displayed by the display device. The thin film transistor includes: a substrate; a gate, a source, a drain and a semiconductor layer formed on the substrate; a first gate protection layer; a gate isolation layer; and a second gate protection layer. The first gate protection layer is at least partly located between the gate and the semiconductor layer, and is an insulating layer. The gate isolation layer is at least partly located between the first gate protection layer and the second gate protection layer, and is a conductive layer. The second gate protection layer is at least partly located between the gate isolation layer and the semiconductor layer, and is an insulating layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9331165-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10504926-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017170309-A1 |
| priorityDate | 2012-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 50.