| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3ed3ad8f844a322be4e471f9e8d7f0ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6d795182f8f0775a891a3a1f78669dd1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_55c25389d7bba318937762088dfb7fc2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e1cd4a20fe64493535d986ccd3a092a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_03f3ffc4306dbdd9fe9ef93b0d7cd7c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c6a79989880fe03cf533b7d6da62b60f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ac1389b04ac2b13bc80e1df8bbd84b0f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2012-07-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a33c3fdee72a21bd188837c2b1c3017c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4b4bd3c8ea767b5ea8444235cb7eb7e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd06c35bc7fc20b662ffaaa2d5ea810f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6fe0bf3e3a0d3edfac7fb17c3c2c3a54
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b7e4d47f9f4ed7d25588b3922aa517d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39772b1ea0f2c5d835be5209048ac8c0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b996e5872e22169e99dc3c516b39bbf1 |
| publicationDate |
2014-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2014015062-A1 |
| titleOfInvention |
Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device |
| abstract |
An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102015109820-B4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9553094-B2 |
| priorityDate |
2012-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |