Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_123d87bcd3dee8aecc18d79f289278de http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0ac7c4778afd1e52a5af8c10e7da44dd http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ee97ec66fcdba4858125c6b24c5bc007 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca43423308f89eb92779f69dbae78f3b |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31 |
filingDate |
2012-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e01820211dcaace3b294fd2021ac12bf http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ffcef42ed5d61a6e0c4ac77f0242559 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a60b242ac1230575a1a8432728253983 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ebde7ba5ebad32e8244c3823345c721 |
publicationDate |
2013-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2013323923-A1 |
titleOfInvention |
Methods for fabricating integrated circuits having improved spacers |
abstract |
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11133180-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018247875-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10658174-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10734238-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10446394-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019103474-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10804099-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10679848-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11011379-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11170997-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10741458-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11646198-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11211253-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10957514-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10515815-B2 |
priorityDate |
2012-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |