| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a29fef702b4d45fd8c7d9a9b4df67402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_dd5e34ff112883b3259b941c4ef75b65
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3d2bfad816bac0bffc5c15e348079f70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6ce9ffce41948cb062486d2c71703465
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_91815133b1460378f4d787d7d4325ef8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_40425d7d1855b0e407dce0e6b58a42e8 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0619
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0634 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2012-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f8b69a19a3e4435a55a594e158ca9a4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f261a3544d1269ba5b194022773d93ae
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_56c5dfb04afb13a09a773df565d0b9b4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8614972307987d56ad1cd8684e8cd1dc |
| publicationDate |
2013-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2013196489-A1 |
| titleOfInvention |
Method for manufacturing deep-trench super pn junctions |
| abstract |
The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material. |
| priorityDate |
2011-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |