http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013093027-A1

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
filingDate 2012-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e9a0d8d9e918fb118e96606ba3a560eb
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publicationDate 2013-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2013093027-A1
titleOfInvention Layout data creation device for creating layout data of pillar-type transistor
abstract A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102014019988-B3
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priorityDate 2011-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 28.