| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b8179f1d1a59f6401f12fe553b449fe5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_64c90008b68804f81d4450ed75558c37
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_997fe98bbc3237ad8a0a4ac09c96b469
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_82a9e22a923eca64a02a97f0dfb493ed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318572 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318513 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-58 |
| filingDate |
2012-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8165c64a741117e6774651775eaac7c6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f69d7009554b026dd84e8b2e461130da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f5ba7936492dba5684c347aa079b15d8 |
| publicationDate |
2013-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2013043897-A1 |
| titleOfInvention |
Testing stacked die |
| abstract |
An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3037833-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11619667-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021302498-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9797949-B2 |
| priorityDate |
2011-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |