| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3efae1572b54c08ba0eefac6438d740a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cea8dbe61b43fd71e0c4025d95ea862d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ab34e598f038996e055866e2143ea56b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13092 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283 |
| filingDate |
2012-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a4e594e1bb011114dec805aecbf29868
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f0025e43fc430972022f736ba5c09ad7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8dbb34456717d623c5b686d86650a5b |
| publicationDate |
2013-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2013012009-A1 |
| titleOfInvention |
Method for self aligned metal gate cmos |
| abstract |
A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9607989-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019108936-A1 |
| priorityDate |
2011-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |