http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013002326-A1

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publicationDate 2013-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2013002326-A1
titleOfInvention Logic circuit and semiconductor device
abstract In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms/cm 3 ) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012313693-A1
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Total number of triples: 30.