| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6eb607bc3fe5247371ae95291f6c7341
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e702746446b52aced7fe3735df4203ef
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_df3bf2ce13cf5d0a16686db5b4e8cf0d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_274556eede6eec7167ecf3cb500e7dfc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06589
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4275
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-50 |
| filingDate |
2011-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee2db2b483447bb891e2473f4dcab45c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce297871be087ace76643aeac22e6d05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52c574c182319396ac7150c770e39071
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9eaf82b0f2e4f5560fc218b479c612b |
| publicationDate |
2012-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012306088-A1 |
| titleOfInvention |
Method and system for internal layer-layer thermal enhancement |
| abstract |
The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016233145-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9754856-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9245836-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11177192-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116364678-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11462512-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11387164-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014001604-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9391011-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8980688-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10937764-B2 |
| priorityDate |
2011-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |