| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f9ad55b72d4944a2c88215e772b46a88
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5034cd79476b964cc8b23643f13ad91b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d231147f38595bbe3114b758cba4a298 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-86
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0203 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06 |
| filingDate |
2012-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_786cc7c0f5448e77d8d564da18d70c1a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9cc57c8b12f9695a2d70b011bd82630f |
| publicationDate |
2012-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012236669-A1 |
| titleOfInvention |
Semiconductor device having compensation capacitance |
| abstract |
Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat. The sense area includes a plurality of sense amplifiers. Each of the sense amplifiers is connected to an associated one or ones of the bit lines. At least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line. At least a part of the compensation capacitance is formed in a same wiring layer as the column selection line. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106711129-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11574660-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11715522-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022415397-A1 |
| priorityDate |
2011-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |