| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ac0f4646b696292e349ef4f572970446
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f4302474fcbaa25974e0da1bc8e3ca53 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 |
| filingDate |
2010-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1acea9374b2676a4c283f66298ea6f5 |
| publicationDate |
2012-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012168842-A1 |
| titleOfInvention |
Split gate flash cell and method for making the same |
| abstract |
A method for forming a split gate flash cell device provides for forming floating gate transistors. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016181435-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11211297-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9653561-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019097027-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014264581-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10734292-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111785723-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108269746-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10546947-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019115266-A1 |
| priorityDate |
2010-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |