http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012127800-A1

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filingDate 2012-01-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2012-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2012127800-A1
titleOfInvention Pair Bit Line Programming To Improve Boost Voltage Clamping
abstract A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10790665-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011194352-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9047962-B2
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