| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f47985b7c371b565f319708450999686
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8c77953ff258d3ad0e26749379802e25
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6f711d029d8ace6fc42ef5655d843fc7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e610eb946b52699c2679f43644663e15 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-361 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356121
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-35613
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-012 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-12 |
| filingDate |
2010-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a65b92a25b9136de194e2ee5609a45c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca8f0c5e23ae6df4d394e1ec9ad37ffb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31f9bb5280043d1db395d345a8855d62 |
| publicationDate |
2012-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012098690-A1 |
| titleOfInvention |
High frequency signal comparator for sha-less analog-to-digital converters |
| abstract |
A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10090992-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I501558-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112260690-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11211922-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9197198-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016294540-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9190987-B2 |
| priorityDate |
2010-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |