| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a5c10ebab6e7029521b9b0e8feb29bb9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_03f3ffc4306dbdd9fe9ef93b0d7cd7c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d0a3d10ed9477633fd2c07c6da61dc49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3ed3ad8f844a322be4e471f9e8d7f0ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6c554f5cf81dce3a5023f07ab02a9f3e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2010-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c314a9157467567ba469fb0bc711274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e192aac5d050784ce9e22c66c47ba13e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5804b1f3cebfe03f1988cab7dc183ef
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f99fd82124025597c580e08c6efad26 |
| publicationDate |
2012-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012021584-A1 |
| titleOfInvention |
Semiconductor device and method for manufacturing the same |
| abstract |
The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove. According to the present invention, the S/D parasitic resistance in the MOS device is reduced, the S/D stress on the channel is increased, the process temperature is lowered, and the process compatibility between the high k gate dielectric layer and the metal gate is improved. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111162087-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111952302-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10128114-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014246734-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8748983-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111180320-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012273886-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017098544-A1 |
| priorityDate |
2010-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |