| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c96b90ad3567877c3e6a75f41050e93b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2884 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 |
| filingDate |
2009-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97003129d407d467574f187da4849bd8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d02eb8d0a77ef459f8dc51345375db2d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_838ad099c6382e2abfc0910e366cea64
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5be170c882f484cd4fd95b5ed4d456bf |
| publicationDate |
2011-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011133747-A1 |
| titleOfInvention |
Integrated electrical circuit and test to determine the integrity of a silicon die |
| abstract |
A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11327050-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10241151-B2 |
| priorityDate |
2009-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |