| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b3310ea86f3c492f6c09d7be6592866d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate |
2011-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e9291cc0eeea975f20ad1adaacf14bb3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c0342e71ef1725281ada87e22a0b740
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_662c65436968f1248f12b1b69c064d7c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd417192be88948f9c0934fa9220d3ae
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_442b48ca2c44f143a876340d1dff5104
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f9b96c47614478ed943cb67afa7a4707 |
| publicationDate |
2011-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011129994-A1 |
| titleOfInvention |
Method of manufacturing a dual face package |
| abstract |
A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10276424-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019005679-A1 |
| priorityDate |
2008-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |