| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d06c7d9d47965fdc46d1f97f633d955
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5a6fb9a4ff477f505e313b2b759dae44 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5635
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5678
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C27-005 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C27-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00 |
| filingDate |
2010-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2c0942bee12d5c22c76939f5d862205b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_799c738bffa5392c80700c7491a7639b |
| publicationDate |
2011-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011110170-A1 |
| titleOfInvention |
Non-volatile memory systems and methods including page read and/or configuration features |
| abstract |
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015279448-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9478275-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013265837-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109088532-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8787100-B2 |
| priorityDate |
1999-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |