| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88d1f8ccd2646a915f17029ff6154147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_71bd5b35267cb4f26b283fe7e36ea336 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-098
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-405
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-808 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 |
| filingDate |
2010-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f8fbf994282f73d0859edcb52764b2d3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67b23ed1792b1cc23bbf79674e815644 |
| publicationDate |
2011-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011068410-A1 |
| titleOfInvention |
Silicon die floorplan with application to high-voltage field effect transistors |
| abstract |
A floorplan for a die having three high-voltage transistors for power applications is described. The three high-voltage transistors are specifically placed in relation to each other to optimize operation. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11152454-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9691762-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106356362-A |
| priorityDate |
2009-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |