| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ad688d029b98a9a0da2cc448581b7ff9 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01019
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0231
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1461
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3128
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14618
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14683 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78 |
| filingDate |
2010-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7932d03e35a3914205efc6cb278dd381 |
| publicationDate |
2011-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011042781-A1 |
| titleOfInvention |
Chip package and fabrication method thereof |
| abstract |
The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110191760-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8791543-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8748949-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011042807-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9281354-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2509296-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9972584-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9419070-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9379174-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016322312-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2509296-A |
| priorityDate |
2009-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |