| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-906 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02071
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23G1-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 |
| filingDate |
2008-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a78562653691fd9149b460fe91cbfc63
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70dacc7ffb318079c0d405e5d91564aa
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa56c8931419f37dbd2e2e3df57e6344 |
| publicationDate |
2010-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2010167514-A1 |
| titleOfInvention |
Post metal gate vt adjust etch clean |
| abstract |
A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8314022-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9005464-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8603837-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014057371-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8945952-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9012322-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014179112-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8716145-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2014105792-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8716146-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2012295431-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9064819-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013095657-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2012162185-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103050374-A |
| priorityDate |
2008-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |