| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a04ec82c01a5765a0fb9c6c0d8a9abba |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-3323 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50 |
| filingDate |
2008-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_716bfacf83313b981930c114846af890 |
| publicationDate |
2010-04-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2010107131-A1 |
| titleOfInvention |
Method and apparatus for memory abstraction and verification using same |
| abstract |
A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11507719-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014195209-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9465898-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015269049-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11416662-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8473883-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9507680-B2 |
| priorityDate |
2008-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |