| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3221 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2009-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c598f74960743a370d926185e50d9112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_19f0d224adf5edd60ef696bd39b50b11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89ad0df3ae4291c94612b5077d4d01f8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a00ce9d5a55c9464556bba6a4f12c24f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9fa09c3bcd929e9f0f0b3d33021384f2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81f89cba86d756fcd330ba2642ab8e64
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b590dee703d282e8b5ea340ee12aa9c2 |
| publicationDate |
2010-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2010068876-A1 |
| titleOfInvention |
Methods of fabricating high-k metal gate devices |
| abstract |
Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011189827-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8877645-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9379198-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11289481-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011227163-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014001566-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9960160-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015200243-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8003461-B1 |
| priorityDate |
2008-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |