| abstract |
Disclosed is a test circuit including a first transfer circuit, a second transfer circuit and comparators and performing parallel testing of a plurality of chips under test. The first transfer circuit includes flip-flops. A data pattern from a tester is supplied to the initial stage chip under test. To the remaining chips under test, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit. |