Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-056 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7853 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7853 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7802 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
filingDate |
2009-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_38208ece55c9bbd29c343ffd7f14f7ad http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89e299310cc67faaf6be10581938ef9c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_997b223dcdbad8660cc6db8c573b8792 |
publicationDate |
2009-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2009317967-A1 |
titleOfInvention |
Semiconductor device having vertical channels and method of manufacturing the same |
abstract |
A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11527653-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023103640-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8624333-B2 |
priorityDate |
2005-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |