| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-763
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7842 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-763
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate |
2009-06-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_23ee2231709742175740addc97004e3a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e45b099ddaac05e2b2742753b8c0a802 |
| publicationDate |
2009-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2009258468-A1 |
| titleOfInvention |
Minimizing transistor variations due to shallow trench isolation stress |
| abstract |
The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor ( 100 ). The method comprises forming an active area ( 105 ) in a substrate ( 115 ), wherein the active area ( 105 ) is bounded by an isolation structure ( 120 ). The method further includes placing at least one stress adjuster ( 130 ) adjacent the active area ( 105 ), wherein the stress adjuster ( 130 ) is positioned to modify a mobility of a majority carrier within a channel region ( 155 ) of the MOS transistor ( 100 ). Other embodiments of the present invention include a MOS transistor device ( 200 ) and a process ( 300 ) for constructing an integrated circuit. |
| priorityDate |
2004-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |