http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009134902-A1

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filingDate 2007-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e09defe2028cb087a9b03bbe32cf717
publicationDate 2009-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2009134902-A1
titleOfInvention Integrated circuit package having reversible esd protection
abstract Methods, systems, and apparatuses are provided for integrated circuit packages and for enabling electrostatic discharge (ESD) testing of the same. A package includes an integrated circuit chip, a substrate, a first electrically conductive trace, and a second electrically conductive trace. The substrate includes a first electrically conductive region and a second electrically conductive region. The first region is coupled to a first ground signal of the chip, and the second region is coupled to a second ground signal of the chip. The first trace is coupled to the first region and the second trace is coupled to the second region. A portion of the first trace is proximate to a portion of the second trace. An electrically conductive material may be deposited to electrically couple the first and second traces to enable ESD protection testing of the package.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10096561-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009262475-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3285293-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9209619-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10359461-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8077439-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9435841-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9869708-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10192798-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014252403-A1
priorityDate 2007-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 42.